Tên khóa học: Verification

Mã số: ICDI

Nội dung đào tạo

• Formal verification & Code Coverage
• Verification Planning
• System Verilog Introduction
• System Verilog Subroutines, Interfaces, Arrays and Queues, Object Oriented Design and Verification.
• System Verilog Randomization, Classes, Coverage.
• System Verilog Assertion Bassed Verification
• UVM Introduction
• UVM Testbench
• UVM Basics (Classes, Phases, Factory, Transaction, Sequence, Driver, Agent, Environment, Test)
• UVM Reporting
• Block Testbench Reuse at Top Level
• VIPs introduction
• Kiểm tra cuối module (trắc nghiệm 30 phút)