Analog IC Design and Layout
Unlike digital design, which involves working with a vast number of transistors, ranging from tens of thousands to millions of gates for a single module/block, analog design typically deals with circuits containing only a few dozen to a few hundred transistors, MOSFETs, resistors, and capacitors per module/cell. In digital design, cells are standardized in size, whereas in analog design, the engineer has full control over the dimensions. As a result, the processes, methods, and tools used for analog design differ significantly from those used in digital design. Although the detailed processes may vary between companies, the overall approach remains similar.
The Analog IC Design & Layout training program at the Phenikaa Semiconductor Training Center is transferred from Synopsys Group, the world’s leading EDA company, ensuring that trainees receive the most advanced knowledge and skills. The course provides comprehensive coverage of Analog IC Design and Layout, from theory to hands-on practice, enabling trainees to confidently address challenges in one of today’s most in-demand fields.
Course Objectives:
Train IC engineers with the knowledge and skills to participate in Analog chip design stages, including schematic design and layout, within an industrial environment.
Course Outcomes:
- Understand the complete chip development process, including design, fabrication, and packaging.
- Gain knowledge of IO cells, ESD protection, and EDA tools;
- Understand semiconductors, various components, CMOS and FinFET structures, and the semiconductor manufacturing cycle;
- Analyze analog circuits from basic to complex designs, including single-/multi-stage amplifiers, current mirrors, op-amps, ADCs, PLLs, and power circuits.
- Perform Analog IC layout, from manual layout to automated layout, for basic circuits as well as complex designs such as op-amps, current mirrors, high-speed circuits,...
- Simulate and verify analog designs at both schematic and layout levels.
- Analyze circuits under different corners, extract parasitic elements, and perform post-layout simulations.
Course Content: Comprises 4 main modules with 40 topics.
Training Duration: 03 months
Tentative Start Date: November–December 2025, or as soon as the minimum class size of 20 trainees is reached.
Tentative Schedule: Three sessions per week from 7:00 PM to 9:00 PM on weekdays, and from 9:00 AM to 5:00 PM on Saturdays. (The schedule may be adjusted to accommodate trainees’ needs and training operations).
Tuition and Additional Information: See here
Instructors:
- Dr. Le Thai Ha;
- Experienced industry experts and lecturers from Synopsys.
- Professors and PhD holders specializing in IC Design.
- Senior S-Phenikaa engineers with extensive experience in complex SoC design.
Facilities & Infrastructure:
- A modern PSTC laboratory capable of supporting simulations for more than 200 trainees simultaneously.
- Industry-grade design tools provided by Synopsys.
Mode of Study: In-person Location: 15th Floor, A10 Building, Phenikaa Semiconductor Training Center, Phenikaa University, Nguyen Van Trac Street, Ha Dong District, Hanoi, Vietnam. Registration Method:
- Online registration and tuition fee payment via: This form
- Or in-person registration at: S-Phenikaa Company Office, 14th Floor, A10 Building, Nguyen Van Trac Street, Ha Dong District, Hanoi, Vietnam.
Application Documents (in the following order):
- 01 copy of graduation diploma or academic transcript;
- 01 copy of National Identification Card;
- 02 passport-sized photos (3×4 cm) for student ID cards (full name, date of birth, and course name written clearly).
For further information about the course, please contact us via email at pstc@phenikaa-uni.edu.vn or by phone at +84 385 353 504.
Detailed Training Program with 4 Modules:
Benefits when participating
Trained by a team of experienced experts and lecturers from Synopsys – the world's leading EDA corporation; Experienced S-Phenikaa engineers in designing complex SoCs and professors specializing in IC Design.
Learners have the opportunity to work at S-Phenikaa or partner IC companies of Phenikaa in Hanoi and receive competitive salaries and benefits for IC design engineers.
Industrial-level design tools provided by Synopsys, ensuring international standard quality.
Learners will have the opportunity to work with world-class simulators such as Zebu 5, Zebu 4, HAPS-100.
Certificate issued and approved by both PSTC and Synopsys (the world's leading EDA corporation) upon graduation.
PSTC practice room is modern, 5-star quality with a capacity of more than 200 students.
Admission Requirements
For candidates with prior knowledge or experience in related fields:
Basic knowledge of Circuit Theory and Electronic Components, and/or an academic background in STEM disciplines, including but not limited to Electrical/Electronic Engineering, Computer Engineering and Information Technology, Communications, Materials Science, Applied Physics, Chemistry, Mechatronics, Mechanical Engineering, Control and Automation, Automotive Engineering, Cryptography, etc.
Language proficiency: Ability to read and understand technical documentation in English.
Other candidates:
Third-year students or above currently enrolled in STEM-related engineering programs at universities or colleges.
Minimum GPA: 2.5/4.0.
Language proficiency: Ability to read and understand technical documentation in English.
Admission eligibility will be reviewed and discussed during the registration process, based on the applicant’s actual knowledge and practical experience.