Course name: IC Synthesis and Optimization

Code: ICS

Training content

• Logic Synthesis – 2 lectures
• Timing and Area Constraints – 2 lectures
• Attributes and Constraints – 5 lectures
• Introduction to Synthesis Design Constraint (SDC) – 1 lectures
• Introduction to scripting languages (Perl & tcl) – 6 lectures
• Synthesis Design Constraint (SDC) with Scripting Languages – 4 lectures
• Compile Strategies – 5 lectures
• Physical Design Introduction (Floorplanning, CTS, PnR, OCV, Power Optimization, PV, Power Estimation) – 4 lectures

Training purpose

• General and practical knowledge of Synthesis and the entire cycle from Logic Synthesis to GDS.

References

• Static Timing Analysis for Nanometer Designs: A Practical Approach
• VLSI Physical Design Automation – Theory and Practice