Digital IC Design Flow

Digital IC Design Flow Course

Course Objectives:

  • To train Digital IC Design Engineers with comprehensive knowledge and integrated skill sets, enabling a full understanding of the Digital Chip design flow. Graduates will be capable of directly participating in all stages of Digital Chip design, from Frontend Design and Verification to Backend Implementation, within an industrial environment.
  • The program also equips engineers with a solid foundation to advance toward Senior Engineer and Lead Engineer roles in the future, offering strong career progression and competitive income potential.

Course Outcomes:

  • Gain a comprehensive understanding of the entire Chip development process, including design, manufacturing, and packaging;
  • Gain knowledge of IO cells, ESD protection, and EDA tools;
  • Understand semiconductors, various components, CMOS and FinFET structures, and the semiconductor manufacturing cycle;
  • Proficient in using Linux/Unix operating systems;
  • Proficient in Verilog programming, with solid knowledge ranging from basic to advanced coding techniques, capable of solving algorithms from simple to relatively complex levels, and able to design code that avoids CDC issues and timing-related problems (such as latch inference, reset issues, etc.);
  • Possess practical skills and understanding of Standard Cell design and simulation;
  • Demonstrate solid skills and knowledge in Verification;
  • Demonstrate solid skills and knowledge in Design for Test (DFT);
  • Possess in-depth skills and strong proficiency in industrial Backend tool flows.

Course Content: Comprises 7 main modules

Training Duration: 3.5 months

Tentative Start Date: March 2025, or upon reaching the minimum required enrollment (20 participants per class)

Tentative Schedule: 03 sessions per week from 19:00 – 21:00 on weekdays and 09:00 – 18:00 on Saturdays.

(The schedule may be adjusted to accommodate trainees’ needs and training operations).

Tuition and Additional Information:  See here

Instructors:

  • Dr. Le Thai Ha;
  • Experienced industry experts and lecturers from Synopsys.
  • Professors and PhD holders specializing in IC Design.
  • Senior S-Phenikaa engineers with extensive experience in complex SoC design.

Facilities & Infrastructure:

  • Zebu 5 and Zebu 4 systems, world-class, currently No.1 in Southeast Asia
  • 02 high-end HAPS-100 systems
  • A modern PSTC laboratory capable of supporting simulations for more than 200 trainees simultaneously.
  • Design tools provided by Synopsys at industrial-grade level
  • High-performance NVIDIA GPU systems, including 8 A100 cards and multiple additional GPUs.

Mode of Study: In-person

Location: 15th Floor, A10 Building, Phenikaa Semiconductor Training Center, Phenikaa University, Nguyen Van Trac Street, Ha Dong District, Hanoi, Vietnam.

Registration Method: 

  • Online registration and tuition fee payment via: This form.
  • Or in-person registration at: S-Phenikaa Company Office, 14th Floor, A10 Building, Nguyen Van Trac Street, Ha Dong District, Hanoi, Vietnam.

Application Documents (in the following order):  

  • 01 copy of graduation diploma or academic transcript;
  • 01 copy of National Identification Card;
  • 02 passport-sized photos (3×4 cm) for student ID cards (full name, date of birth, and course name written clearly).

For further information about the course, please contact us via email at pstc@phenikaa-uni.edu.vn or by phone at +84 385 353 504.

Detailed Training Program with 7 Modules:

Group 428

Verilog Introduction
Group 428

IC Design Introduction
Group 428

Linux, Unix Introduction
Group 428

Digital Standard Cell Introduction
Group 428

Verification Introduction
Group 428

Design For Test Introduction
Group 428

Synthesis and Physical Backend

Benefits when participating

Trained by a team of experienced experts and lecturers from Synopsys – the world's leading EDA corporation; Experienced S-Phenikaa engineers in designing complex SoCs and professors specializing in IC Design.

Learners have the opportunity to work at S-Phenikaa or partner IC companies of Phenikaa in Hanoi and receive competitive salaries and benefits for IC design engineers.

Industrial-level design tools provided by Synopsys, ensuring international standard quality.

Learners will have the opportunity to work with world-class simulators such as Zebu 5, Zebu 4, HAPS-100.

Certificate issued and approved by both PSTC and Synopsys (the world's leading EDA corporation) upon graduation.

PSTC practice room is modern, 5-star quality with a capacity of more than 200 students.

Doi tuong hoc vien

Admission Requirements

For candidates with prior knowledge or experience in related fields:
Possess basic knowledge of Circuit Theory and Electronic Components, and/or have an academic or professional background in STEM disciplines (Electrical/Electronic Engineering, Computer Engineering and Information Technology, Materials Science, Applied Physics, Chemistry, Mechatronics, Mechanical Engineering, Control and Automation, Automotive Engineering, Cryptography, etc.).

Language proficiency: Ability to read and understand technical documentation in English.

Other candidates:
Third-year students or above currently enrolled in STEM-related engineering programs at universities or colleges.

Minimum GPA: 2.5/4.0.

Language proficiency: Ability to read and understand technical documentation in English.

Admission eligibility will be reviewed and discussed during the registration process, based on the applicant’s actual knowledge and practical experience.