Verification

IC Verification Design Course

Course Objectives: To train IC Verification Engineers with sufficient knowledge and practical skills to directly participate in the Chip verification process in an industrial environment, and to enable engineers to progress toward Senior Engineer and Lead Engineer roles in the future with competitive income potential.

Course Outcomes:

  • Understand the complete chip development process, including design, fabrication, and packaging.
  • Proficient in using Linux/Unix operating systems;
  • Possess basic Verilog programming skills, with the ability to read, understand, and debug code, as well as to design and simulate basic functional blocks;
  • Understand and be proficient in SystemVerilog;
  • Understand various Verification methodologies and be able to develop Verification Plans;
  • Be capable of SystemVerilog programming for Digital Chip verification, including testbench creation, environment setup, reporting, and assertions;
  • Possess skills in working with UVM, including environment setup, testbench reuse from Block level to Top level, reporting, and analysis of test cases, scenarios, and coverage;
  • Demonstrate strong proficiency in industrial-grade verification tool flows.

Course Content: Includes 5 main modules

Training Duration: 03 months

Tentative Start Date: May–June 2025, or upon reaching the minimum required enrollment (20 trainees per class).

Tentative Schedule: Three sessions per week from 7:00 PM to 9:00 PM on weekdays, and from 9:00 AM to 5:00 PM on Saturdays.

(The schedule may be adjusted to accommodate trainees’ needs and training operations).

Tuition and Additional Information: See here

Instructors:

  • Dr. Le Thai Ha;
  • Experienced industry experts and lecturers from Synopsys.
  • Professors and PhD holders specializing in IC Design.
  • Senior S-Phenikaa engineers with extensive experience in complex SoC design.

Facilities & Infrastructure:

  • Zebu 5 and Zebu 4 systems, world-class, currently No.1 in Southeast Asia
  • 02 high-end HAPS-100 systems
  • A modern PSTC laboratory capable of supporting simulations for more than 200 trainees simultaneously.
  • Design tools provided by Synopsys at industrial-grade level
  • High-performance NVIDIA GPU systems, including 8 A100 cards and multiple additional GPUs.

Mode of Study: In-person

Location: 15th Floor, A10 Building, Phenikaa Semiconductor Training Center, Phenikaa University, Nguyen Van Trac Street, Ha Dong District, Hanoi, Vietnam.

Registration Method: 

  • Online registration and tuition fee payment via: This form
  • Or in-person registration at: S-Phenikaa Company Office, 14th Floor, A10 Building, Nguyen Van Trac Street, Ha Dong District, Hanoi, Vietnam.

Application Documents (in the following order):  

  • 01 copy of graduation diploma or academic transcript;
  • 01 copy of National Identification Card;
  • 02 passport-sized photos (3×4 cm) for student ID cards (full name, date of birth, and course name written clearly).

For further information about the course, please contact us via email at pstc@phenikaa-uni.edu.vn or by phone at +84 385 353 504.

Detailed Training Program with 5 Modules:

Group 428

IC Design Introduction
Group 428

Linux, Unix Introduction
Group 428

Verilog Introduction
Group 428

Verification
Group 428

Advanced Verification with Zebu

Benefits when participating

Trained by a team of experienced experts and lecturers from Synopsys – the world's leading EDA corporation; Experienced S-Phenikaa engineers in designing complex SoCs and professors specializing in IC Design.

Learners have the opportunity to work at S-Phenikaa or partner IC companies of Phenikaa in Hanoi and receive competitive salaries and benefits for IC design engineers.

Industrial-level design tools provided by Synopsys, ensuring international standard quality.

Learners will have the opportunity to work with world-class simulators such as Zebu 5, Zebu 4, HAPS-100.

Certificate issued and approved by both PSTC and Synopsys (the world's leading EDA corporation) upon graduation.

PSTC practice room is modern, 5-star quality with a capacity of more than 200 students.

Doi tuong hoc vien

Admission Requirements

For candidates with prior knowledge or experience in related fields:
Basic knowledge of Circuit Theory and Electronic Components, and/or an academic background in STEM disciplines, including but not limited to Electrical/Electronic Engineering, Computer Engineering and Information Technology, Communications, Materials Science, Applied Physics, Chemistry, Mechatronics, Mechanical Engineering, Control and Automation, Automotive Engineering, Cryptography, etc.

Language proficiency: Ability to read and understand technical documentation in English.

Other candidates:
Third-year students or above currently enrolled in STEM-related engineering programs at universities or colleges.

Minimum GPA: 2.5/4.0.

Language proficiency: Ability to read and understand technical documentation in English.

Admission eligibility will be reviewed and discussed during the registration process, based on the applicant’s actual knowledge and practical experience.